The present invention generally relates to semiconductor devices and more particularly to a semiconductor memory device having a ferroelectric capacitor.
Semiconductor devices such as DRAMs and SRAMs are used extensively in various information processing apparatuses including computers as a high-speed main memory device. These conventional semiconductor devices, however, are volatile in nature and the information stored therein is lost when the electric power is turned off. Thus, it has been practiced in conventional computers and computer systems to use magnetic disk devices as a large capacity, auxiliary storage device for storing programs and data.
However, magnetic disk devices are bulky and fragile, and are inherently vulnerable to mechanical shocks. Further, magnetic disk devices generally have drawbacks of large electrical power consumption and low access speed.
In view of the problems noted above, there is an increasing tendency in computers and computer systems of using flash-memory devices for the non-volatile auxiliary storage device. A flash-memory device is a device having a construction similar to that of a MOS transistor and stores information in an insulated floating gate in the form of electrical charges. It should be noted that flash-memory devices have a construction suitable for monolithic integration on a semiconductor chip in the form of an LSI. Thus, there are attempts to construct a large-capacity storage device comparable to a magnetic disk device by using a flash-memory.
In a flash-memory device, writing of information is achieved by tunneling of hot electrons through a tunneling insulation film into the floating gate electrode. Further, erasing of the information is achieved also by causing the electrons in the floating gate to tunnel to a source region or to a channel region through the tunneling insulation film. Thus, a flash-memory device has an inherent drawback in that it takes a substantial time for writing or erasing information. Further, a flash-memory device generally shows the problem of deterioration of the tunneling insulation film after a repeated writing and erasing operations. When the tunneling insulation film is deteriorated, the reading or erasing operation becomes unstable and unreliable. An EEPROM, having a similar construction to a flash-memory, has a similar problem.
In view of the various drawbacks of the foregoing conventional non-volatile semiconductor devices, there is a proposal of a ferroelectric semiconductor memory device designated hereinafter as FeRAM for the auxiliary memory device and further for the high-speed main memory device of a computer. A ferroelectric semiconductor memory device stores information in a ferroelectric capacitor insulation film in the form of spontaneous polarization.
A ferroelectric semiconductor memory device typically includes a memory cell transistor and a memory cell capacitor similarly to a DRAM, wherein the memory cell capacitor uses a ferroelectric material such as PZT (Pb(Zr,Ti)O3) or PLZT ((Pb,La)(Zr,Ti)O3) for the capacitor insulation film. Thus, the ferroelectric semiconductor memory device is suitable for monolithic integration to form an LSI.
As the ferroelectric semiconductor memory device carries out the writing of information by controlling the spontaneous polarization of the ferroelectric capacitor insulation film, the writing is achieved with a high speed, faster by a factor of 1000 or more than the case of a flash-memory. As noted before, the writing of information is achieved in a flash-memory by injecting hot electrons into the floating gate through the tunneling insulation film. As the control of the polarization is achieved by simply applying a voltage, the power consumption is also reduced below about 1/10 as compared with the case of a flash-memory. Further, the ferroelectric semiconductor memory device, lacking the tunneling insulation film, provides an increased lifetime of one hundred thousand times as large as the lifetime of a flash-memory device.
Currently, FeRAMs are fabricated according to a relatively easy design rule of about 1 μm. On the other hand, investigation is being made for increasing the tightness of the design rule so as to enable integration of the FeRAMs with other high-speed submicron devices such as CMOS logic devices on a common semiconductor chip.
FIG. 1 shows the construction of a conventional FeRAM 10.
Referring to FIG. 1, the FeRAM 10 includes a memory cell transistor constructed on a Si substrate 11, which may be any of the p-type or n-type. The half of the cell structure is represented in FIG. 1, wherein it should be noted that the process used in FIG. 1 is nothing more than an ordinary CMOS process. Thus, a p-type well 11A is formed on a Si substrate 11, on which an active region is defined by a field oxide film 12. On the Si substrate 11, there is provided a gate electrode 13 in correspondence to the foregoing active region, wherein the gate electrode 13 constitutes the word line of the FeRAM. Further, a gate oxide film not illustrated is interposed between the Si substrate 11 and the gate electrode 13, and diffusion regions 11B and 11C of the n+-type are formed in the p-type well 11A at both lateral sides of the gate electrode 13 as the source region and the drain region of the memory cell transistor. Thereby, a channel region is formed in the p-type well 11A between the diffusion region 11B and the diffusion region 11C.
It should be noted that the gate electrode 13 is covered by a CVD oxide film 14 provided so as to cover the surface of the Si substrate 11 in correspondence to the active region. A lower electrode 15 having a Pt/Ti structure is deposited on the CVD oxide film 14, wherein the lower electrode 15 constitutes the drive line of the FeRAM.
A ferroelectric insulation film 16 of PZT or PLZT covers the lower electrode 15, and an upper electrode 17 of Pt is formed on the ferroelectric capacitor insulation film 16.
It should be noted that the lower electrode 15, the ferroelectric insulation film 16 and the upper electrode 17 form together a ferroelectric capacitor. The ferroelectric capacitor as a whole is covered by another interlayer insulation film 18.
A contact hole 18A is formed in the interlayer insulation film 18 so as to expose the upper electrode 17, and contact holes 18B and 18C are formed further in the interlayer insulation films 18 and 14 so as to expose the diffusion regions 11B and 11C, respectively.
The local interconnection pattern 19A is formed by an Al-alloy such that the local interconnection pattern 19A connects the contact hole 18A and the contact hole 18B electrically.
There is provided a bit line pattern 19B of an Al-alloy on the interlayer insulation film 18 so as to make an electrical contact with the diffusion region 11C at the contact hole 18C. The local interconnection pattern 19A and the bit line 19B are covered by a passivation film 20.
FIG. 2 shows the hysteresis appearing in the polarization of a PLZT film constituting the foregoing ferroelectric capacitor insulation film 16.
Referring to FIG. 2, it will be noted that the PLZT film 16 experiences an inversion of polarization when a predetermined write voltage is applied between the lower electrode 15 and the upper electrode 17 such that a predetermined electric field is applied to the PLZT film 16. In other words, desired information is written into the PLZT film 16 in the form of binary data by applying the write voltage across the upper electrode 17 and the lower electrode 15. Further, reading of the information thus written into the PLZT film 16 is achieved by detecting the conduction or no-conduction of the memory cell transistor, wherein such a detection is made by activating the foregoing word line, and hence the gate electrode 13, and further by detecting the voltage appearing at the bit line electrode 19B.
Larger the value of the spontaneous polarization represented in FIG. 2 by 2 Pr, the more the reliability of the retention of information in the PLZT film 16. Further, the magnitude of the electric field needed to cause a writing of information decreases with increasing value of 2 Pr. In other words, increase of the spontaneous polarization 2 Pr contributes to the decrease of the drive voltage of the FeRAM 10. Thus, there is a demand for increasing the value of the spontaneous polarization 2 Pr in the FeRAM 10 of FIG. 1.
It should be noted that the semiconductor memory device of FIG. 1 can be used also for a DRAM. In this case, due to the very large relative dielectric constant of the ferroelectric capacitor insulation film 16, a sufficient capacitance is secured without using a complicated shape and process for forming the memory cell capacitor.
In general, it is known that the ferroelectric properties of a PZT or PLZT film is related to the orientation of the PZT or PLZT crystals constituting the film. Commonly, a predominantly <111>- or <100>-orientation is obtained for a PZT or PLZT film formed on a Pt lower electrode, which has a self-textured <111>-orientation, due to the epitaxial effect, in which the surface energy is minimized as a result of the foregoing film orientation. It should be noted that a PZT or PLZT film has a self-textured <100>-orientation. In order to maximize the remnant polarization of the PZT or PLZT film, it is desired to align the PZT of PLZT crystals, which belong to the tetragonal crystal system, such that the switching direction for the preferential <100> orientation is perpendicular to the switching electric field.
Meanwhile, it is known that the PZT or PLZT film constituting the ferroelectric capacitor insulation film 16 of FIG. 1 shows a columnar microstructure and that the value of the spontaneous polarization 2 Pr is maximized when the crystal grains therein are oriented in the <111> direction.
In the formation of the ferroelectric capacitor as noted above, it is very important to crystallize the ferroelectric capacitor insulation film 16 by conducting a crystallization process. Without such a crystallization process, no desirable property is obtained for the ferroelectric capacitor.
Conventionally, such a ferroelectric capacitor is formed first by forming the adhesion layer of the Ti and then the lower electrode 15 of Pt by a sputtering process conducted on the interlayer insulation film 14 in a reducing atmosphere. Next, the ferroelectric capacitor insulation film 16 of PZT or PLZT is formed on the lower electrode 15 by a sputtering process or a sol-gel process.
Next, the ferroelectric capacitor insulation film 16 is subjected to a thermal annealing process in an oxidizing atmosphere at a temperature of typically 700-800° C., and the ferroelectric capacitor insulation film 16 thus formed undergoes a crystallization. Thereby, it has been practiced to conduct the crystallization process in an oxidizing atmosphere so that the formation of oxygen defects in the ferroelectric capacitor insulation film 16, caused as a result of diffusion of oxygen atoms from the ferroelectric capacitor insulation film 16 to the lower electrode 15, is successfully compensated for. As a result of the crystallization, the ferroelectric capacitor insulation film 16 shows a preferable hysteresis as represented in FIG. 2, with a spontaneous polarization 2 Pr.
On the other hand, in such a process of crystallizing the ferroelectric capacitor insulation film 16, it has been discovered that there occurs an extensive counter diffusion of Pt and O at the boundary between the lower Pt electrode 15 and the ferroelectric capacitor insulation film 16. More specifically, Pt from the lower electrode 15 penetrates into the ferroelectric capacitor insulation film 16 and O from the ferroelectric capacitor insulation film 16 penetrates into the lower electrode 15.
In order to avoid the foregoing problem of mutual diffusion, it is proposed to crystallize the ferroelectric capacitor insulation film 16 by RTA processes first conducted in an inert atmosphere and then conducted in an oxidizing atmosphere. By conducting the first RTA process in an inert atmosphere, the lower electrode 15 undergoes densification and the foregoing problem of counter diffusion of Pt and O is effectively suppressed.
Further, such a two-step annealing process suppresses the migration of Ti from the Ti adhesion layer to the surface of the lower electrode 15 through the grain boundary of Pt crystals constituting the lower electrode 15, wherein the Ti atoms thus reached the surface of the lower electrode 15 act as a nuclei for the <100> growth of the ferroelectric capacitor insulation film 16.
On the other hand, in the experimental investigation on such a ferroelectric capacitor formed by the two-step annealing process has revealed the fact that the ferroelectric capacitor insulation film thus formed tend to show a peeling, particularly in the marginal part of the semiconductor wafer where there is a shadow ring for preventing deposition of Pt on such marginal part of the semiconductor wafer. It should be noted that the semiconductor wafer is covered by a Ti film uniformly, while the deposition of Pt on such marginal part is prevented by the shadow ring so as to avoid unwanted deposition of Pt to the rear side of the wafer. As a result of the use of the shadow ring, the thickness of the Pt film constituting the lower electrode 15 decreases toward the marginal part of the semiconductor wafer, while it is noted that the problem of the peeling of the ferroelectric capacitor insulation film 16 occurs preferentially on such marginal part of the semiconductor wafer.
When such peeling occurs, the yield of production of the semiconductor device is deteriorated substantially.